Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. A via is typically a metal plug which extends through an insulative layer. A barrier layer is used to protect the via from metal diffusion and from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, it is characteristic of metals at very high current density and temperatures of 100° C. or more.
Integrated circuit manufacturers have attempted to reduce via resistance as the via size decreases by reducing the thickness of the barrier material. According to one conventional process, plasma vapor deposition (PVD), IC manufacturers deposit a very thin barrier material at the bottom of the via due to non-conformed deposition. The thickness of the barrier material is reduced by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. These advanced deposition processes form hightly conformed barrier metal films. However, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration.
FIGS. 1A and 1B illustrate a schematic cross-sectional view of a portion 100 of an integrated circuit including a copper layer 110, a copper via 120, a copper layer 130, a dielectric layer 150, and a dielectric layer 160. Via 120 and copper layer 130 are separated by a barrier layer 140.
Portion 100 also includes a dielectric layer 142 that is separated from copper layer 130 by an etch stop layer 174. Dielectric layer 142 can be oxide and etch stop layer 174 can be Silicon Nitride (SiN). Etch stop layer 174 prevents diffusion of copper from copper layer 130 into dielectric layer 142. Dielectric layer 150 can be separated from copper layer 130 by a barrier layer 152. Similarly, dielectric layer 160 can be separated from copper layer 110 by a barrier layer 182. Barrier layers 152 and 182 can be Tantalum Nitride (TaN). Etch stop layers 172, 174, 176, and 178 can be Silicon Nitride (SiN).
According to conventional processes, barrier layer 140 can have a cross-sectional thickness of between 7 nm to 25 nm. Barrier layer 140 inhibits diffusion of copper ions from layers into via 120 and from via into dielectric layer 142. Conventional barrier layers can include Tantalum Nitride (TaN).
FIG. 1A shows a portion formed according to a single damascene process where copper layer 110 and copper via 120 are deposited in two separate steps and are separated by a barrier section 182. FIG. 1B shows a portion formed according to a dual damascene process where copper layer 110 and copper via 120 are deposited in one step or process and are not separated by a barrier.
As discussed above, conventional systems have attempted to reduce the thickness of barrier layer 140 to reduce the resistance associated with via 120. However, this reduction in thickness can cause electromigration failures. FIGS. 2A and 2B illustrate portion 100 described with reference to FIGS. 1A and 1B, further having an EM failure or void 145 in copper layer 130. FIG. 2A shows a portion formed according to a single damascene process (as described with reference to FIG. 1A) where copper layer 110 and copper via 120 are formed in two separate steps or processes. FIG. 2B shows a portion formed according to a dual damascene process (as described with reference to FIG. 1B) where copper layer 110 and copper via 120 are formed in one step or process.
FIGS. 3A and 3B illustrate portion 100 having an EM failure or void 155 in via 120 due to copper diffusion from copper via layer 120. FIG. 3A shows a portion formed according to a single damascene process (as described with reference to FIG. 1A) where copper layer 110 and copper via 120 are formed in two separate steps or processes. FIG. 3B shows a portion formed according to a dual damascene process (as described with reference to FIG. 1B) where copper layer 110 and copper via 120 are formed in one step or process.
EM failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264-65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
Thus, there is a need for an interconnect or via having less resistance while not experiencing electromigration in via or line failures. Further, there is a need for a method of forming a large grain size interconnect having stuffed grain boundaries for high electromigration reliability. Even further, there is a need for a method of using ternary copper alloy to obtain a low resistance and large grain size interconnect.